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Review of Techniques and Architectures used to achieve Breakdown Voltage up to 50V in LDMOS
Hardik M. Khodifad*, Alpesh Dafda

Published in: International Journal of Scientific Review and Research in Engineering and Technology
Volume- 1, Issue-3, pp.123-134, Apr 2016
DPI :-> 16.10069.IJSRRET.2016.V1I3.123134.1309



Abstract
This paper presents comparative approach to the different designs and implementation of LDMOS used to achieve high breakdown voltage. The designs are compared from various perspectives that include breakdown voltage, on resistance, reliability, device dimensions, drain current, gate voltage. Various graphs are shown to observe and verify the results. The design methods are mainly focusing at drift region to provide high breakdown voltage. So, in this paper, some of these techniques are discussed to provide overall picture of improving breakdown voltage in LDMOS

Key-Words / Index Term
High Voltage, LDMOS, Breakdown Voltage

How to cite this article
Hardik M. Khodifad*, Alpesh Dafda , “Review of Techniques and Architectures used to achieve Breakdown Voltage up to 50V in LDMOS”, International Journal of Scientific Review and Research in Engineering and Technology, 1, Issue-3, pp.123-134, Apr 2016. DPI:16.10069.IJSRRET.V1.I3.1309